9.0 TEST BIT FILE
A test file is provided as a download from the DLP Design website that provides rudimentary access
to the I/O features of the DLP-HS-FPGA. The following features are provided:
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Ping
Read the High/Low State of the Input-Only Pins
Drive I/O Pins High/Low or Read their High/Low State
Simple Loopback on Channel B
4 Byte Read/Write Access of Row, Column, and Bank Address in the DDR2 SDRAM
This bit file is available from the DLP-HS-FPGA’s download page. The command structure that
supports these features is explained in Section 11.
Rev. 1.7 (May 2011)
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? DLP Design, Inc.